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Full Publication List

Journal Papers

  1. Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, and Kenichi Okada, “A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3672–3687, Dec. 2018. [Open Access, Link]
  2. Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Zheng Li, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, and Kenichi Okada, “A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio,” IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1228–1242, May 2019. [Link]
  3. Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 265-μW Fractional-N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3478–3492, Dec. 2019. [Open Access, Link]
  4. Bangan Liu, Yuncheng Zhang, Junjun Qiu, Hongye Huang, Zheng Sun, Dingxin Xu, Haosheng Zhang, Yun Wang, Jian Pang, Zheng Li, Xi Fu, Atsushi Shirane, Hitoshi Kurosu, Yoshinori Nakane, Shunichiro Masaki, and Kenichi Okada, “A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5 nm CMOS,” IEEE Solid-State Circuits Letters, vol. 3, pp. 34–37, Jan. 2020. [Link]
  5. Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Bangan Liu, Aravind Tharayil Narayanan, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, and Kenichi Okada, “A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,” IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2371–2386, Sep. 2020. [Open Access, Link]
  6. Zheng Sun, Dingxin Xu, Hongye Huang, Zheng Li, Hanli Liu, Bangan Liu, Jian Pang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A compact TF-based LC-VCO with ultra-low-power operation and supply pushing reduction for IoT applications,” IEICE Transactions on Electronics, vol. E103.C, no. 10, pp. 505–513, Oct 2020. [Link]
  7. Zheng Sun, Hanli Liu, Hongye Huang, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang, Rui Wu, Wei Deng, Atsushi Shirane, and Kenichi Okada, “A 0.85 mm² BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 168, no. 1, pp. 196–209, Jan. 2021. [Link]
  8. Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, and Kenichi Okada, “A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems,” IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1310–1326, April 2021. [Open Access, Link]
  9. Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A Low-Jitter Injection-Locked Clock Multiplier Using 97-μW Transformer-Based VCO with 18-kHz Flicker Noise Corner,” IEICE Transactions on Electronics, vol. E104.C, no. 7, pp. 289–299, July 2021. [Link]
  10. Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Masaya Miyahara, Atsushi Shirane, and Kenichi Okada, “A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth,” IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3741–3755, Dec. 2021. [Open Access, Link]
  11. Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, and Kenichi Okada, “A time-mode-modulation digital quadrature power amplifier based on 1-bit delta–sigma modulator and hybrid FIR filter,” IEEE Journal of Solid-State Circuits, vol. 59, no. 4, pp. 993–1005, April 2024, doi: 10.1109/JSSC.2023.3349002. [Open Access, Link]
  12. Hóngyè Huáng, Bangan Liu, Zezheng Liu, Dingxin Xu, Yuncheng Zhang, Waleed Madany, Junjun Qiu, Zheng Sun, Ashbir Aviat Fadila, Jian Pang, Zheng Li, Dongwon You, Atsushi Shirane, and Kenichi Okada, “A fully synthesizable fractional-N MDLL with energy efficient ring-oscillator-based DTC of large tuning range,” IEEE Solid-State Circuits Letters, vol. 7, pp. 54–57, 2024, doi: 10.1109/LSSC.2024.3352736. [Open Access, Link]
  13. Dingxin Xu, Zheng Sun, Yuang Xiong, Yuncheng Zhang, Hongye Huang, Zezheng Liu, Ashbir Aviat Fadila, Atsushi Shirane, and Kenichi Okada, “ A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network,” IEEE Solid-State Circuits Letters, vol. 7, pp. 171–174, 2024, doi: 10.1109/LSSC.2024.3399228. [Open Access, Link]

International Conference Papers (Peer-Reviewed)

  1. Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, and Akira Matsuzawa, “28.2 An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS,” 2018 International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 444–446, Feb 14, 2018. [Link]
  2. Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Tsuyoshi Miura, Daiki Matsumoto, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, and Kenichi Okada, “A 28GHz CMOS Phased-Array Transceiver Featuring Gain Invariance Based on LO Phase Shifting Architecture with 0.1-Degree Beam-Steering Resolution for 5G New Radio,” 2018 IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, USA, pp. 56–59, June 11, 2018. [Link]
  3. Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, and Kenichi Okada, “A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver,” 44th European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, pp. 310–333, Sep 6, 2018. [Link]
  4. Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “16.1 A 265µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,” 2019 International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 256–257, Feb 19, 2019. [Link]
  5. Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Aravind Tharayil Narayanan, Bangan Liu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, and Kenichi Okada, “21.1 A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,” 2019 International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 344–345, Feb 20, 2019. [Link]
  6. Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO,” 45th European Solid-State Circuits Conference (ESSCIRC), Kraków, Poland, Sep 24, 2019. [Link]
  7. Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, and Kenichi Okada, “A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR,” 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, pp. 5–6, Jan 13, 2020. [Link]
  8. Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, and Kenichi Okada, “A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth,” 2021 International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 454–456, Feb 18, 2021,doi: 10.1109/ISSCC42613.2021.9365861. [Link]
  9. Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Weichu Chen, Yun Wang, Dongwon You, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, and Kenichi Okada, “A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation,” 2021 Symposium on VLSI Circuits, Kyoto, Japan, pp. 1-2, Jun 17, 2021, doi: 10.23919/VLSICircuits52068.2021.9492496. [Link]
  10. Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang, Hongye Huang, Hanli Liu, Bangan Liu, Zheng Li, Jian Pang, Atsushi Shirane, and Kenichi Okada, “A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration,” ESSCIRC 2021 – IEEE 47th European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, pp. 499-502, Sep 2021, doi: 10.1109/ESSCIRC53450.2021.9567781. [Link]
  11. Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, and Kenichi Okada, “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration,” 2023 International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 80-82, Feb 2023, doi: 10.1109/ISSCC42615.2023.10067516. [Link]
  12. Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Atsushi Shirane, and Kenichi Okada, “A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path,” ESSCIRC 2023- IEEE 49th European Solid-State Circuits Conference (ESSCIRC), Lisbon, Portugal, pp. 265-268, Sep 2023, doi: 10.1109/ESSCIRC59616.2023.10268737. [Link]
  13. Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, and Kenichi Okada, “A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter,” 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 192-194, doi: 10.1109/ISSCC49657.2024.10454284. [Link]

Conference Papers in Japan (Not Peer-Reviewed)

  1. Hongye Huang, Zheng Sun, Hanli Liu, Dexian Tang, Kenichi Okada, and Akira Matsuzawa, “Current-reuse LNA for Low Power 2.4-GHz Receivers,” 電子情報通信学会総合大会, 東京, 2018年3月20日.
  2. Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Kenichi Okada, and Akira Matsuzawa, “An ADPLL-based High Interference Tolerant BLE Receiver with DAC Feedback Loop,” 電子情報通信学会総合大会, 東京, 2018年3月20日.
  3. Dexian Tang, Hanli Liu, Zheng Sun, Hongye Huang, Kenichi Okada, and Akira Matsuzawa, “An Isolated Constant-slope Digital-to-Time Converter,” 電子情報通信学会総合大会, 東京, 2018年3月21日.
  4. Hongye Huang, Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Atsushi Shirane, and Kenichi Okada, “An Ultra-Low-Power Fractional-N All-Digital PLL Using 10-bit Isolated Constant-Slope Digital-to-Time Converter,” 電子情報通信学会LSIとシステムのワークショップ, 東京, 2018年5月15日.
  5. Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Atsushi Shirane, and Kenichi Okada, “An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,” 電子情報通信学会LSIとシステムのワークショップ, 東京, 2018年5月15日.
  6. Zheng Sun, Hanli Liu, Hongye Huang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A High Dynamic Range BLE Front-End with On-Chip Matching Network,” 電子情報通信学会ソサイエティ大会, 金沢, 2018年9月14日.
  7. Hongye Huang, Zheng Sun, Hanli Liu, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 2.6mW BLE Transmitter Front-End with Fully-Passive Harmonic Suppression,” 電子情報通信学会ソサイエティ大会, 金沢, 2018年9月14日.
  8. Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Aravind Tharayil Narayanan, Bangan Liu, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, and Kenichi Okada, “A 28GHz CMOS Bi-Directional Phased-Array Beamformer for 5G NR Supporting Dual-Polarized MIMO,” 集積回路研究会, 石垣, 2019年3月14日.
  9. Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver,” 集積回路研究会, 石垣, 2019年3月15日.
  10. Hongye Huang, Hanli Liu, Zheng Sun, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs,” 集積回路研究会, 石垣, 2019年3月15日.
  11. Hongye Huang, Hanli Liu, Zheng Sun, Dingxin Xu, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 2.4GHz Low-Power Subsampling/Sampling-Mixed Fractional-N All-Digital PLL,” 電子情報通信学会ソサイエティ大会, 大阪, 2019年9月10日.
  12. Zheng Sun, Dingxin Xu, Hongye Huang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO,” 電子情報通信学会ソサイエティ大会, 大阪, 2019年9月10日.
  13. Dingxin Xu, Zheng Sun, Hongye Huang, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A Time-Amplifier Gain Calibration Technique for ADPLL,” 電子情報通信学会ソサイエティ大会, 大阪, 2019年9月10日.
  14. Daxu Zhang, Yuncheng Zhang, Hongye Huang, Dingxin Xu, Atsushi Shirane, and Kenichi Okada, “A Multi-Phase Frequency Synthesizer with Injection-Locking Ring Oscillator,” 電子情報通信学会 総合大会 (於 広島大学), C-12-29, March 2024.
  15. Zezheng Liu, Hongye Huang, Yuncheng Zhang, Atsushi Shirane, and Kenichi Okada, “A Nonlinearity Compensation Technique for Digital-to-Time Converter in All-Digital PLLs,” 電子情報通信学会 総合大会 (於 広島大学), C-12-31, March 2024.
  16. Waleed Madany, Hongye Huang, Bangan Liu, Atsushi Shirane, and Kenichi Okada, “A Fully Synthesizable DPLL for Spread Spectrum Clock Generation,” 電子情報通信学会 総合大会 (於 広島大学), C-12-32, March 2024.

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