Double-Edge-Triggered JK-Flipflop

In Roland E. Best’s famous PLL book, he mentioned a kind of interesting circuit called “JK-flipflop phase detectors”.

If a rising edge comes to J, then Q will output “1”; if a rising edge comes to K, then Q will output “0”.

This is an ideal circuit if we want to control one signal by using two signals. However, Best did not provide the actual implementation of the JK-flipflop phase detector. Also, most of the standard cells do not provide it. If we write behavioral Verilog/VHDL code, we can get an error during synthesis.

Intuitively, we can think of a circuit with two pulse generators at the input and a J-K latch (or S-R latch) at the output. However, this is quite dangerous. If we want the circuit to behave correctly, we may shorten the generated pulses, but shorter pulses lead to the requirement of large slew rate. This kind of implementation is quite “dirty”. Let us think of another example, almost no one uses a pulse generator and a D-latch to build a D-flipflop.

After hours of re-inventing and Duckduckgo-ing, I found an implementation in Sam Palermo’s slides as shown below:

If a rising edge comes to J, the voltage level of net 1 and net 2 becomes different, and then leads to “1” at the output of the XOR gate; similarly, a rising edge of K results in the same voltage level of net 1 and net 2, and makes the XOR gate outputs “0”.

Metastability should be concerned with this structure. If the interval between the rising edges of J and K is less than the gate delay of the D-flipflop, it will cause unintended output.

The most important concern of this circuit is probably the name. In Best’s book, it is called “JK-flipflop phase detector”. We cannot simply call it “JK-flipflop” or “J-K flip-flop” because this is the name of another circuit with a J-K latch and a clock input, and we cannot call it “phase detector” because it may probably have nothing to do with phase detection depending on different applications. Maybe as my title suggests, “double-edge-triggered JK-flipflop” or “double-edge-triggered SR-flipflop” could be good names.